Design for Test and Testability

Design for Test and TestabilityHours: 3 0 3

Logic simulation, fault modeling, fault simulation, algorithms and techniques for automatic test pattern generation in combinational and sequential circuits (Algorithm, PODEM, recursive learning), design error/fault diagnosis, introduction to functional testing of microprocessors, ALUs and memories, design for testability, and logic and scan built-in self-test.

Pre-requisites: NoneCo-requisites: None

Hours: XYZ where X = Lecture, Y = Lab, Z = Credit
All hours are per week.
3 Lab hours constitute 1 credit hour
1 credit hour implies 1 lecture of 50mins per academic week. 16 weeks in total.
Pre-Requisite courses are courses required to be completed before this course may be taken
Co-Requisite courses are courses required to be taken along with this course

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